Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
A transceiver includes a transmitter and a receiver. The transceiver typically operates with at least two clock signals, a transmit clock signal (TCLK) and a sampling clock signal. The TCLK signal is used by the transmitter to regulate transmission of data symbols. The sampling clock signal is used by the receiver to regulate sampling of the received signal.
Synchronous systems depend on precise clock distribution for high performance. Clock skew is defined as the difference in time between simultaneous clock transitions within a system. Clock networks must be designed to minimize skew or the differences in delay throughout a clocking network. The ideal is that every component that needs clocking should receive the edge of the clock at the same time within each clock period. Fully synchronous designs require this methodology and are highly recommended since they can tolerate higher clock rates and make it easier to perform timing analysis. Synchronous operation means that all of the devices that need clocks in the system use the same clock signal. To ensure that the network operates as closely to the ideal as possible, the skew must be minimized along the entire clocking network. This ensures that all sequential elements see a common clock edge.
Traditional multi-gigabit transceiver designs use integrated transmit and receive buffers to handle the inherent phase difference between clock domains, such as between the physical coding sublayer (PCS) and the physical media attachment (PMA) clock domains or between the FPGA fabric and transceiver. These buffers introduce both latency and uncertainty to both the transmit and receive data paths. Thus, such buffers are undesirable for many applications. Such problems may occur between other boundaries.
Furthermore, in channel-bonded applications where multiple outputs are bonded to provide a single channel, skew between multiple outputs must be controlled. With a large number of transceivers on a chip and with programmable clock routing, maintaining the alignment of multiple outputs can be difficult. Transmit outputs of multiple transceivers must be deskewed or skewed to compensate for misalignment.
It can be seen then that there is a need for a method and apparatus for providing clocking phase alignment in a transceiver system.